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Opus Card – DDR-2 Interface

Reference Manual

12/03/2010 07:35 AM 4

1.4 DDR-2 Memory Accessible by the CPU

The DDR-2 memory is 128 MBytes in size, organized as 32-bit words. The memory is

accessible from 0x88000000 to 0x8FFFFFFF.

The C_CACHLINE_ADDR_MODE for the PLB interface in the DDR-2 memory controller

MUST be set to 1 so that cache line bursts always start at the first address in the cache line. A

setting of 0, which is the default, will not work with the current implementation of the DDR-2

memory controller.

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Digilent DDR-2 Opus Card Manuale Utente Pagina 4